PCI Express® (PCIe) Designs: Test, Debug and Verification
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The need for greater I/O bandwidth in the computer industry has caused designers to shift from using parallel buses like ISA, PCI and PCI-X to using multi-lane serial interconnects running at Gigabit speed. The industry has settled on PCI Express® technology as the key I/O technology of the future, as it delivers on the higher bandwidth requirements, helps to reduce cost for silicon vendors and leverages the software environment from the pervasive PCI/PCIX® technology. While the change from parallel buses to multi-lane serial buses sounds like a small step, it presented a whole set of new debug and validation challenges to designers.
Serial technology requires a different approach to testing, starting from the physical layer and moving up through the transaction layer. In many cases, the parallel bus had several slots connected to the same physical lines, which allowed you to connect test equipment to the same bus and monitor other devices. With the point-to-point nature of serial technologies, this is no longer possible, and with the speed moving from the megahertz range to the gigahertz range, probing of the signal becomes a real challenge.