Practical Analysis of Backplane Vias
白皮书
It is well established that often, the largest impedance discontinuity in a high speed serial interconnect is from the vias used when the signal changes layers. Signal vias are typically placed anywhere in a design to optimize routing density and especially at connectors. These vias can be a dominate source of degradation of the eye diagram.
The measured differential insertion loss of two different differential vias in a 26 layer board is shown in the cover figure. In addition, a cross section of the vias is shown to illustrate the two important features of a through hole via: the through path and the residual stub.
The presence of the via stub causes resonances in the differential insertion loss, which can significantly detract from the insertion loss if the via stub is very short. While stub lengths can be minimized, they can never be completely eliminated. In order to evaluate the impact of an arbitrary length via stub and the impact of the through part of the via on performance, a scalable model which accurately accounts for these effects is essential. Such a model can be used to explore design space and balance design tradeoffs.
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