!!!!    6    0    1  719694616   0000                                         

!-----------------------------------------------------------------------
!  Copyright (c) Hewlett-Packard Co. 1992
!
!  All Rights Reserved.  Reproduction, adaptation, or translation
!  without prior written permission is prohibited, except as allowed
!  under the copyright laws.
!
!-----------------------------------------------------------------------
!
! Device:        27c210
! Manufacturer:
! Description:   64k x 16 bit PROM
! Package:       44 pin PLCC
! Test Platform: 3065,3070
! Safeguard:     standard_ttl
!
!-----------------------------------------------------------------------
!
! Additional Comments:
!
!-----------------------------------------------------------------------

sequential

receive delay  400n
vector cycle   500n

assign   VCC                  to pins  43,44
assign   GND                  to pins  12,34
assign   VPP                  to pins   2

assign   Address              to pins  41,40,39,38,37,36,35,32,31,30,29,28
assign   Address              to pins   27,26,25,24

assign   Data                 to pins  4,5,6,7,8,9,10,11,14,15,16,17,18,19,20,21

assign   Chip_Enable_bar      to pins  3
assign   Output_Enable_bar    to pins  22





power    VCC, GND, VPP

family   TTL

inputs   Chip_Enable_bar, Output_Enable_bar
inputs   Address
outputs  Data

format   hexadecimal    Address
format   hexadecimal    Data

disable  Data  with  Output_Enable_bar to "1"
disable  Data  with  Chip_Enable_bar   to "1"

when     Output_Enable_bar is "1"   inactive Data
when     Chip_Enable_bar   is "1"   inactive Data

trace    Data  to Address, Chip_Enable_bar, Output_Enable_bar

!***********************************************************************
!***********************************************************************

vector  Initialize
   set   Chip_Enable_bar      to "0"
   set   Output_Enable_bar    to "0"
   set   Address              to "0000"
end vector

vector  Keep_Control
   set   Chip_Enable_bar      to "k"
   set   Output_Enable_bar    to "k"
   set   Address              to "kkkk"
end vector

vector  Lower_Address
   initialize                 to Keep_Control
   set   Data                 to "0000"
   set   Address              to "0000"
   upcounter   Address
end vector

vector  Upper_Address
   initialize                 to Keep_Control
   set   Data                 to "0000"
   set   Address              to "7fff"
   downcounter Address
end vector

vector  Chip_Enable_false
   initialize                 to Keep_Control
   set   Chip_Enable_bar      to "1"
end vector

vector  Output_Enable_false
   initialize                 to Keep_Control
   set   Output_Enable_bar    to "1"
end vector

vector  CE_false_OE_false
   initialize                 to Keep_Control
   set   Chip_Enable_bar      to "1"
   set   Output_Enable_bar    to "1"
end vector

vector  Enable_test_1
   initialize                 to Keep_Control
   set   Data                 to "xxxx"            !!! Specify an address and
   set   Address              to "0000"            !!! its known contents.
end vector

vector  Enable_test_2
   initialize                 to Keep_Control
   set   Data                 to "xxxx"            !!! Specify an address and
   set   Address              to "7fff"            !!! its known contents.
end vector

!***********************************************************************
!***********************************************************************

unit  "Test lower 256 memory locations"
   execute  Initialize

   preset counter    Lower_Address  compress
   repeat   255 times     !!!   Repeat 16383 times to test entire EPROM contents
      count    Lower_Address        compress
   end repeat
end unit

unit  "Test upper 256 memory locations"
   execute  Initialize

   preset counter    Upper_Address  compress
   repeat   255 times     !!!   Repeat 16383 times to test entire EPROM contents
      count    Upper_Address        compress
   end repeat
end unit

warning  "Chip_Enable_bar and Output_Enable_bar are not tested."
warning  "Unit disable tests are provided but are commented."
warning  "User modification of the test is required to test these pins."

!!!   The following unit disable tests for Chip_Enable_bar and
!!!   Output_Enable_bar may be uncommented; however, these units will
!!!   fail unless the vectors "Enable_test_1" and "Enable_test_2" are
!!!   modified to specify known addresses on the EPROM and the appropriate
!!!   contents of those addresses.  The addresses must be programmed and
!!!   they should not contain all 1's or all 0's.  The contents of the
!!!   two addresses must differ.
!!!
!!!unit disable test "Test Chip_Enable_bar"
!!!   execute  Initialize
!!!   execute  Chip_Enable_false
!!!
!!!   execute  Enable_test_1
!!!   execute  Enable_test_2
!!!   execute  Enable_test_1
!!!end unit
!!!
!!!unit disable test "Test Output_Enable_bar"
!!!   execute  Initialize
!!!   execute  Output_Enable_false
!!!
!!!   execute  Enable_test_1
!!!   execute  Enable_test_2
!!!   execute  Enable_test_1
!!!end unit
!!!
!!!unit disable test "Test Chip_Enable_bar and Output_Enable_bar (tied)"
!!!   tied  Chip_Enable_bar, Output_Enable_bar
!!!   execute  Initialize
!!!   execute  CE_false_OE_false
!!!
!!!   execute  Enable_test_1
!!!   execute  Enable_test_2
!!!   execute  Enable_test_1
!!!end unit

!
!  End of test
!