!!!!    6    0    1  986749944  Va9c6                                         

! Device           : 74ls208
! Function         : Static RAM 3-state 256 x 4
! revision         : B.01.00
! safeguard        : high_out_lsttl
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

sequential

! warning "Pull-ups are required to test high-impedance outputs."

assign  VCC         to pins 20
assign  GND         to pins 10

assign  Data_input  to pins 19,5,9,11
assign  Data_output to pins 15,14,13,12
assign  Address     to pins 18,8,7,6,4,3,2,1

assign  Data_in_D0  to pins 11   !AT Added for minimum pin test.
assign  Data_in_D1  to pins 9    !AT Added for minimum pin test.
assign  Data_in_D2  to pins 5    !AT Added for minimum pin test.
assign  Data_in_D3  to pins 19   !AT Added for minimum pin test.

assign  Data_out_D0 to pins 12   !AT Added for minimum pin test.
assign  Data_out_D1 to pins 13   !AT Added for minimum pin test.
assign  Data_out_D2 to pins 14   !AT Added for minimum pin test.
assign  Data_out_D3 to pins 15   !AT Added for minimum pin test.

assign  Write_enable  to pins 17
assign  Output_enable_bar to pins 16

family  TTL

power   VCC, GND

inputs Data_input, Address, Write_enable, Output_enable_bar
inputs Data_in_D0, Data_in_D1, Data_in_D2, Data_in_D3      !AT Added for min pin test.

outputs Data_output
outputs Data_out_D0, Data_out_D1, Data_out_D2, Data_out_D3 !AT Added for min pin test.

when  Output_enable_bar is "1"   inactive Data_output

trace Data_output to  Data_input, Address, Write_enable, Output_enable_bar

disable Data_output  with Output_enable_bar  to "1"


!*********************************************************************
!*********************************************************************

vector    Address_00000000
     set  Write_enable        to "0"
     set  Output_enable_bar   to "1"
     set  Address             to "00000000"
end vector

vector    Address_00000001
     set  Write_enable        to "0"
     set  Output_enable_bar   to "1"
     set  Address             to "00000001"
end vector

vector    Address_00000011
     set  Write_enable        to "0"
     set  Output_enable_bar   to "1"
     set  Address             to "00000011"
end vector

vector    Address_00000111
     set  Write_enable        to "0"
     set  Output_enable_bar   to "1"
     set  Address             to "00000111"
end vector

vector    Address_00001111
     set  Write_enable        to "0"
     set  Output_enable_bar   to "1"
     set  Address             to "00001111"
end vector

vector    Address_00011111
     set  Write_enable        to "0"
     set  Output_enable_bar   to "1"
     set  Address             to "00011111"
end vector

vector    Address_00111111
     set  Write_enable        to "0"
     set  Output_enable_bar   to "1"
     set  Address             to "00111111"
end vector

vector    Address_01111111
     set  Write_enable        to "0"
     set  Output_enable_bar   to "1"
     set  Address             to "01111111"
end vector

vector    Address_11111111
     set  Write_enable        to "0"
     set  Output_enable_bar   to "1"
     set  Address             to "11111111"
end vector

vector    Output_enable_high
     set  Write_enable        to "0"
     set  Output_enable_bar   to "1"
end vector

vector    Read_data_0000
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "0000"
end vector

vector    Read_data_0001
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "0001"
end vector

vector    Read_data_0010
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "0010"
end vector

vector    Read_data_0011
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "0011"
end vector

vector    Read_data_0100
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "0100"
end vector

vector    Read_data_0101
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "0101"
end vector

vector    Read_data_0110
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "0110"
end vector

vector    Read_data_0111
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "0111"
end vector

vector    Read_data_1000
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "1000"
end vector

vector    Read_data_1001
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "1001"
end vector

vector    Read_data_1010
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "1010"
end vector

vector    Read_data_1011
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "1011"
end vector

vector    Read_data_1100
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "1100"
end vector

vector    Read_data_1101
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "1101"
end vector

vector    Read_data_1110
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "1110"
end vector

vector    Read_data_1111
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_output         to "1111"
end vector

vector    Write_data_0000
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "0000"
end vector

vector    Write_data_0001
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "0001"
end vector

vector    Write_data_0010
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "0010"
end vector

vector    Write_data_0011
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "0011"
end vector

vector    Write_data_0100
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "0100"
end vector

vector    Write_data_0101
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "0101"
end vector

vector    Write_data_0110
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "0110"
end vector

vector    Write_data_0111
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "0111"
end vector

vector    Write_data_1000
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "1000"
end vector

vector    Write_data_1001
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "1001"
end vector

vector    Write_data_1010
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "1010"
end vector

vector    Write_data_1011
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "1011"
end vector

vector    Write_data_1100
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "1100"
end vector

vector    Write_data_1101
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "1101"
end vector

vector    Write_data_1110
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "1110"
end vector

vector    Write_data_1111
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "1111"
end vector

vector    Write_enable_high
     set  Output_enable_bar   to "1"
     set  Address             to "kkkkkkkk"
     set  Data_input          to "kkkk"
     set  Write_enable        to "1"
end vector

vector    Write_enable_low
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

vector    Read_data_D0_0
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_out_D0         to "0"
end vector

vector    Read_data_D0_1
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_out_D0         to "1"
end vector

vector    Read_data_D1_0
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_out_D1         to "0"
end vector

vector    Read_data_D1_1
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_out_D1         to "1"
end vector

vector    Read_data_D2_0
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_out_D2         to "0"
end vector

vector    Read_data_D2_1
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_out_D2         to "1"
end vector

vector    Read_data_D3_0
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_out_D3         to "0"
end vector

vector    Read_data_D3_1
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Output_enable_bar   to "0"
     set  Data_out_D3         to "1"
end vector

vector    Write_data_D0_0
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_in_D0          to "0"
end vector

vector    Write_data_D0_1
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_in_D0          to "1"
end vector

vector    Write_data_D1_0
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_in_D1          to "0"
end vector

vector    Write_data_D1_1
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_in_D1          to "1"
end vector

vector    Write_data_D2_0
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_in_D2          to "0"
end vector

vector    Write_data_D2_1
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_in_D2          to "1"
end vector

vector    Write_data_D3_0
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_in_D3          to "0"
end vector

vector    Write_data_D3_1
     set  Output_enable_bar   to "1"
     set  Write_enable        to "0"
     set  Address             to "kkkkkkkk"
     set  Data_in_D3          to "1"
end vector

vector    WE_high_D0
     set  Output_enable_bar   to "1"
     set  Address             to "kkkkkkkk"
     set  Data_in_D0          to "k"
     set  Write_enable        to "1"
end vector

vector    WE_high_D1
     set  Output_enable_bar   to "1"
     set  Address             to "kkkkkkkk"
     set  Data_in_D1          to "k"
     set  Write_enable        to "1"
end vector

vector    WE_high_D2
     set  Output_enable_bar   to "1"
     set  Address             to "kkkkkkkk"
     set  Data_in_D2          to "k"
     set  Write_enable        to "1"
end vector

vector    WE_high_D3
     set  Output_enable_bar   to "1"
     set  Address             to "kkkkkkkk"
     set  Data_in_D3          to "k"
     set  Write_enable        to "1"
end vector

!*********************************************************************
!*********************************************************************

sub  Write_data (Address, Data)
     execute   Address
     execute   Data
     execute   Write_enable_high
     execute   Write_enable_low
end sub

sub  Read_data (Address, Data)
     execute   Address
     execute   Data
     execute   Output_enable_high
end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutine "Write_data" reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus. The subroutine "Read_data" did not
!AT require any modification as all references to the data bus are made
!AT via a passed parameter (Data). This reference can be modified in the
!AT call statement.

sub  Write_data_Dx (Address, Data_Dx, WE_high_Dx)
     execute   Address
     execute   Data_Dx
     execute   WE_high_Dx
     execute   Write_enable_low
end sub

!*********************************************************************

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

    call Write_data_Dx (Address_00000000,Write_data_D0_0, WE_high_D0)
    call Read_data (Address_00000000,Read_data_D0_0)

    call Write_data_Dx (Address_00000000,Write_data_D0_1, WE_high_D0)
    call Read_data (Address_00000000,Read_data_D0_1)

end unit

unit   "awaretest D1 Test"

    call Write_data_Dx (Address_00000000,Write_data_D1_0, WE_high_D1)
    call Read_data (Address_00000000,Read_data_D1_0)

    call Write_data_Dx (Address_00000000,Write_data_D1_1, WE_high_D1)
    call Read_data (Address_00000000,Read_data_D1_1)

end unit

unit   "awaretest D2 Test"

    call Write_data_Dx (Address_00000000,Write_data_D2_0, WE_high_D2)
    call Read_data (Address_00000000,Read_data_D2_0)

    call Write_data_Dx (Address_00000000,Write_data_D2_1, WE_high_D2)
    call Read_data (Address_00000000,Read_data_D2_1)

end unit

unit   "awaretest D3 Test"

    call Write_data_Dx (Address_00000000,Write_data_D3_0, WE_high_D3)
    call Read_data (Address_00000000,Read_data_D3_0)

    call Write_data_Dx (Address_00000000,Write_data_D3_1, WE_high_D3)
    call Read_data (Address_00000000,Read_data_D3_1)

end unit

unit "test RAM"

     call Write_data (Address_00000000, Write_data_0000)
     call Write_data (Address_00000001, Write_data_0001)
     call Write_data (Address_00000011, Write_data_0011)
     call Write_data (Address_00000111, Write_data_0010)
     call Write_data (Address_00001111, Write_data_0110)
     call Write_data (Address_00011111, Write_data_0111)
     call Write_data (Address_00111111, Write_data_0101)
     call Write_data (Address_01111111, Write_data_0100)
     call Write_data (Address_11111111, Write_data_1100)

     call Read_data (Address_00000000, Read_data_0000)
     call Read_data (Address_00000001, Read_data_0001)
     call Read_data (Address_00000011, Read_data_0011)
     call Read_data (Address_00000111, Read_data_0010)
     call Read_data (Address_00001111, Read_data_0110)
     call Read_data (Address_00011111, Read_data_0111)
     call Read_data (Address_00111111, Read_data_0101)
     call Read_data (Address_01111111, Read_data_0100)
     call Read_data (Address_11111111, Read_data_1100)

     call Write_data (Address_00000000, Write_data_1111)
     call Write_data (Address_00000001, Write_data_1110)
     call Write_data (Address_00000011, Write_data_1100)
     call Write_data (Address_00000111, Write_data_1101)
     call Write_data (Address_00001111, Write_data_1001)
     call Write_data (Address_00011111, Write_data_1000)
     call Write_data (Address_00111111, Write_data_1010)
     call Write_data (Address_01111111, Write_data_1011)
     call Write_data (Address_11111111, Write_data_0011)

     call Read_data (Address_00000000, Read_data_1111)
     call Read_data (Address_00000001, Read_data_1110)
     call Read_data (Address_00000011, Read_data_1100)
     call Read_data (Address_00000111, Read_data_1101)
     call Read_data (Address_00001111, Read_data_1001)
     call Read_data (Address_00011111, Read_data_1000)
     call Read_data (Address_00111111, Read_data_1010)
     call Read_data (Address_01111111, Read_data_1011)
     call Read_data (Address_11111111, Read_data_0011)

end unit

!    End of test