!!!!    6    0    1  986861544  V35c0                                         

! Device           : mcm6290
! Function         : Static RAM 16k x 4
! revision         : B.01.00
! safeguard        : high_out_cmos
! Modifications    : Modified for AwareTest xi
!
  warning           "This library has not been verified with hardware."

 ! In this revision  Address_High and Address_Low are not considered as
 ! seperate vectors. In the same vectore we set both Address_High and
 ! Address_Low.
 ! Advangtage is we need not have a seperate "kk" and subroutine also
 ! becomes simpler.
 !
 sequential

 assign  VCC                      to pins 24
 assign  GND                     to pins 12

 assign  Chip_Enable_Bar         to pins 10
 assign  Output_Enable_Bar       to pins 11
 assign  Write_Enable_Bar        to pins 13

 assign  Address_High        to pins 23, 22
 assign  Address_Low         to pins 21,20,19,9,8,7,6,5,4,3,2,1

 assign  Data_Bus                to pins 17, 16, 15, 14
 assign  Data_D0                 to pins 14   !AT Added for minimum pin test.
 assign  Data_D1                 to pins 15   !AT Added for minimum pin test.
 assign  Data_D2                 to pins 16   !AT Added for minimum pin test.
 assign  Data_D3                 to pins 17   !AT Added for minimum pin test.

 assign  NC                      to pins 18


 power   VCC, GND

 family  TTL

 inputs  Chip_Enable_Bar, Output_Enable_Bar, Write_Enable_Bar
 inputs  Address_High, Address_Low

 bidirectional Data_Bus
 bidirectional Data_D0, Data_D1, Data_D2, Data_D3 !AT Added for min. pin test.

 nondigital   NC

 format  hexadecimal Address_Low, Data_Bus

 disable Data_Bus with Chip_Enable_Bar    to "1"
 disable Data_Bus with Output_Enable_Bar  to "1"

 trace Data_Bus to Address_High, Address_Low,Chip_Enable_Bar
 trace Data_Bus to Output_Enable_Bar, Write_Enable_Bar

 ! vector definitions

 !  ****************************************************************

 vector Init_State
    set Chip_Enable_Bar           to "0"
    set Output_Enable_Bar         to "0"
 end vector

 vector Keep_State
    drive Data_bus
    set Chip_Enable_Bar           to "k"
    set Output_Enable_Bar         to "k"
    set Write_Enable_bar          to "k"
    set Address_High              to "kk"
    set Address_Low               to "kkk"
    set Data_bus                  to "k"
 end vector

 vector Chip_Enable
    initialize to  Keep_State
    set Chip_Enable_Bar           to "0"
 end vector

 vector Chip_Disable
    initialize to  Keep_State
    set Chip_Enable_Bar           to "1"
 end vector

 vector Output_Enable
    initialize to  Keep_State
    set Output_Enable_Bar         to "0"
 end vector

 vector Output_Disable
    initialize to  Keep_State
    set Output_Enable_Bar         to "1"
 end vector

 vector Write_Enable
    initialize to  Keep_State
    set Write_Enable_Bar          to "0"
 end vector

 vector Write_Disable
    initialize to  Keep_State
    set Write_Enable_Bar          to "1"
 end vector

 vector Read_Enable
    initialize to  Keep_State
    set Write_Enable_Bar          to "1"
 end vector

 vector Address_Bus_00_000
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "000"
 end vector

 vector Address_Bus_00_001
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "001"
 end vector

 vector Address_Bus_00_002
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "002"
 end vector

 vector Address_Bus_00_004
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "004"
 end vector

 vector Address_Bus_00_008
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "008"
 end vector

 vector Address_Bus_00_010
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "010"
 end vector

 vector Address_Bus_00_020
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "020"
 end vector

 vector Address_Bus_00_040
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "040"
 end vector

 vector Address_Bus_00_080
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "080"
 end vector

 vector Address_Bus_00_100
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "100"
 end vector

 vector Address_Bus_00_200
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "200"
 end vector

 vector Address_Bus_00_400
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "400"
 end vector

 vector Address_Bus_00_800
    initialize to  Keep_State
    set Address_High              to "00"
    set Address_Low               to "800"
 end vector

 vector Address_Bus_01_000
    initialize to  Keep_State
    set Address_High              to "01"
    set Address_Low               to "000"
 end vector

 vector Address_Bus_10_000
    initialize to  Keep_State
    set Address_High              to "10"
    set Address_Low               to "000"
 end vector

 vector Data_D_0
    initialize to  Keep_State
    set Data_Bus                  to "0"
 end vector

 vector Data_D_1
    initialize to  Keep_State
    set Data_Bus                  to "1"
 end vector

 vector Data_D_2
    initialize to  Keep_State
    set Data_Bus                  to "2"
 end vector

 vector Data_D_3
    initialize to  Keep_State
    set Data_Bus                  to "3"
 end vector

 vector Data_D_4
    initialize to  Keep_State
    set Data_Bus                  to "4"
 end vector

 vector Data_D_5
    initialize to  Keep_State
    set Data_Bus                  to "5"
 end vector

 vector Data_D_6
    initialize to  Keep_State
    set Data_Bus                  to "6"
 end vector

 vector Data_D_7
    initialize to  Keep_State
    set Data_Bus                  to "7"
 end vector

 vector Data_D_8
    initialize to  Keep_State
    set Data_Bus                  to "8"
 end vector

 vector Data_D_9
    initialize to  Keep_State
    set Data_Bus                  to "9"
 end vector

 vector Data_D_A
    initialize to  Keep_State
    set Data_Bus                  to "A"
 end vector

 vector Data_D_B
    initialize to  Keep_State
    set Data_Bus                  to "B"
 end vector

 vector Data_D_C
    initialize to  Keep_State
    set Data_Bus                  to "C"
 end vector

 vector Data_D_D
    initialize to  Keep_State
    set Data_Bus                  to "D"
 end vector

 vector Data_D_E
    initialize to  Keep_State
    set Data_Bus                  to "E"
 end vector

 vector Data_D_F
    initialize to  Keep_State
    set Data_Bus                  to "F"
 end vector

 vector Data_R_x
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "x"
 end vector

 vector Data_R_0
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "0"
 end vector

 vector Data_R_1
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "1"
 end vector

 vector Data_R_2
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "2"
 end vector

 vector Data_R_3
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "3"
 end vector

 vector Data_R_4
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "4"
 end vector

 vector Data_R_5
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "5"
 end vector

 vector Data_R_6
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "6"
 end vector

 vector Data_R_7
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "7"
 end vector

 vector Data_R_8
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "8"
 end vector

 vector Data_R_9
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "9"
 end vector

 vector Data_R_A
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "A"
 end vector

 vector Data_R_B
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "B"
 end vector

 vector Data_R_C
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "C"
 end vector

 vector Data_R_D
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "D"
 end vector

 vector Data_R_E
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "E"
 end vector

 vector Data_R_F
    initialize to  Keep_State
    receive Data_Bus
    set Data_Bus                  to "F"
 end vector

!AT The following vectors have been added for a minimum pins test. Any
!AT vectors that references the data bus was copied and modified to reference
!AT only a single pin of the data bus.

 vector Keep_State_D0
    drive Data_D0
    set Chip_Enable_Bar           to "k"
    set Output_Enable_Bar         to "k"
    set Write_Enable_bar          to "k"
    set Address_High              to "kk"
    set Address_Low               to "kkk"
    set Data_D0                   to "k"
 end vector

 vector Address_00_000_D0
    initialize to  Keep_State_D0
    set Address_High              to "00"
    set Address_Low               to "000"
 end vector

 vector Write_Enable_D0
    initialize to  Keep_State_D0
    set Write_Enable_Bar          to "0"
 end vector

 vector Write_Disable_D0
    initialize to  Keep_State_D0
    set Write_Enable_Bar          to "1"
 end vector

 vector Data_D0_0
    initialize to  Keep_State_D0
    set Data_D0                   to "0"
 end vector

 vector Data_D0_1
    initialize to  Keep_State_D0
    set Data_D0                   to "1"
 end vector

 vector Read_Enable_D0
    initialize to  Keep_State_D0
    set Write_Enable_Bar          to "1"
 end vector

 vector Data_RD0_x
    initialize to  Keep_State_D0
    receive Data_D0
    set Data_D0                   to "x"
 end vector

 vector Data_RD0_0
    initialize to  Keep_State_D0
    receive Data_D0
    set Data_D0                   to "0"
 end vector

 vector Data_RD0_1
    initialize to  Keep_State_D0
    receive Data_D0
    set Data_D0                   to "1"
 end vector

 vector Keep_State_D1
    drive Data_D1
    set Chip_Enable_Bar           to "k"
    set Output_Enable_Bar         to "k"
    set Write_Enable_bar          to "k"
    set Address_High              to "kk"
    set Address_Low               to "kkk"
    set Data_D1                   to "k"
 end vector

 vector Address_00_000_D1
    initialize to  Keep_State_D1
    set Address_High              to "00"
    set Address_Low               to "000"
 end vector

 vector Write_Enable_D1
    initialize to  Keep_State_D1
    set Write_Enable_Bar          to "0"
 end vector

 vector Write_Disable_D1
    initialize to  Keep_State_D1
    set Write_Enable_Bar          to "1"
 end vector

 vector Data_D1_0
    initialize to  Keep_State_D1
    set Data_D1                   to "0"
 end vector

 vector Data_D1_1
    initialize to  Keep_State_D1
    set Data_D1                   to "1"
 end vector

 vector Read_Enable_D1
    initialize to  Keep_State_D1
    set Write_Enable_Bar          to "1"
 end vector

 vector Data_RD1_x
    initialize to  Keep_State_D1
    receive Data_D1
    set Data_D1                   to "x"
 end vector

 vector Data_RD1_0
    initialize to  Keep_State_D1
    receive Data_D1
    set Data_D1                   to "0"
 end vector

 vector Data_RD1_1
    initialize to  Keep_State_D1
    receive Data_D1
    set Data_D1                   to "1"
 end vector

 vector Keep_State_D2
    drive Data_D2
    set Chip_Enable_Bar           to "k"
    set Output_Enable_Bar         to "k"
    set Write_Enable_bar          to "k"
    set Address_High              to "kk"
    set Address_Low               to "kkk"
    set Data_D2                   to "k"
 end vector

 vector Address_00_000_D2
    initialize to  Keep_State_D2
    set Address_High              to "00"
    set Address_Low               to "000"
 end vector

 vector Write_Enable_D2
    initialize to  Keep_State_D2
    set Write_Enable_Bar          to "0"
 end vector

 vector Write_Disable_D2
    initialize to  Keep_State_D2
    set Write_Enable_Bar          to "1"
 end vector

 vector Data_D2_0
    initialize to  Keep_State_D2
    set Data_D2                   to "0"
 end vector

 vector Data_D2_1
    initialize to  Keep_State_D2
    set Data_D2                   to "1"
 end vector

 vector Read_Enable_D2
    initialize to  Keep_State_D2
    set Write_Enable_Bar          to "1"
 end vector

 vector Data_RD2_x
    initialize to  Keep_State_D2
    receive Data_D2
    set Data_D2                   to "x"
 end vector

 vector Data_RD2_0
    initialize to  Keep_State_D2
    receive Data_D2
    set Data_D2                   to "0"
 end vector

 vector Data_RD2_1
    initialize to  Keep_State_D2
    receive Data_D2
    set Data_D2                   to "1"
 end vector

 vector Keep_State_D3
    drive Data_D3
    set Chip_Enable_Bar           to "k"
    set Output_Enable_Bar         to "k"
    set Write_Enable_bar          to "k"
    set Address_High              to "kk"
    set Address_Low               to "kkk"
    set Data_D3                   to "k"
 end vector

 vector Address_00_000_D3
    initialize to  Keep_State_D3
    set Address_High              to "00"
    set Address_Low               to "000"
 end vector

 vector Write_Enable_D3
    initialize to  Keep_State_D3
    set Write_Enable_Bar          to "0"
 end vector

 vector Write_Disable_D3
    initialize to  Keep_State_D3
    set Write_Enable_Bar          to "1"
 end vector

 vector Data_D3_0
    initialize to  Keep_State_D3
    set Data_D3                   to "0"
 end vector

 vector Data_D3_1
    initialize to  Keep_State_D3
    set Data_D3                   to "1"
 end vector

 vector Read_Enable_D3
    initialize to  Keep_State_D3
    set Write_Enable_Bar          to "1"
 end vector

 vector Data_RD3_x
    initialize to  Keep_State_D3
    receive Data_D3
    set Data_D3                   to "x"
 end vector

 vector Data_RD3_0
    initialize to  Keep_State_D3
    receive Data_D3
    set Data_D3                   to "0"
 end vector

 vector Data_RD3_1
    initialize to  Keep_State_D3
    receive Data_D3
    set Data_D3                   to "1"
 end vector

 !  Sub definitions

 sub Write(Address, Data)
    execute Address
    execute Write_Enable
    execute Data
    execute Write_Disable
 end sub

 sub Read(Address ,Data)
    execute Address
    execute Read_Enable
    execute Data_R_x
    execute Data
 end sub

!AT The following subroutines have been added for a minimum pins test.
!AT Vectors in the subroutines reference the entire data bus.
!AT Therefore this subroutine was copied and modified to reference only
!AT a single pin of the data bus.

 sub Write_Dx(Address, Write_Enable, Data, Write_Disable)
    execute Address
    execute Write_Enable
    execute Data
    execute Write_Disable
 end sub

 sub Read_Dx(Address, Read_Enable, Data_R_x, Data)
    execute Address
    execute Read_Enable
    execute Data_R_x
    execute Data
 end sub

 !  Unit Definitions

 !  Check Address and Data lines
 !  The following pattern of Address_Bus and Data_Bus Write/Read
 !  tests for an address pin stuck to Hi and also for address pins
 !  are stuck together.

!AT The following AwareTest units have been added for minimum pins tests. Each
!AT unit tests a separate data pin starting with D0.

unit   "awaretest D0 Test"

 execute Init_State

 call Write_Dx (Address_00_000_D0, Write_Enable_D0, Data_D0_0, Write_Disable_D0)
 call Read_Dx  (Address_00_000_D0, Read_Enable_D0, Data_RD0_x, Data_RD0_0)

 call Write_Dx (Address_00_000_D0, Write_Enable_D0, Data_D0_1, Write_Disable_D0)
 call Read_Dx  (Address_00_000_D0, Read_Enable_D0, Data_RD0_x, Data_RD0_1)

end unit

unit   "awaretest D1 Test"

 execute Init_State

 call Write_Dx (Address_00_000_D1, Write_Enable_D1, Data_D1_0, Write_Disable_D1)
 call Read_Dx  (Address_00_000_D1, Read_Enable_D1, Data_RD1_x, Data_RD1_0)

 call Write_Dx (Address_00_000_D1, Write_Enable_D1, Data_D1_1, Write_Disable_D1)
 call Read_Dx  (Address_00_000_D1, Read_Enable_D1, Data_RD1_x, Data_RD1_1)

end unit

unit   "awaretest D2 Test"

 execute Init_State

 call Write_Dx (Address_00_000_D2, Write_Enable_D2, Data_D2_0, Write_Disable_D2)
 call Read_Dx  (Address_00_000_D2, Read_Enable_D2, Data_RD2_x, Data_RD2_0)

 call Write_Dx (Address_00_000_D2, Write_Enable_D2, Data_D2_1, Write_Disable_D2)
 call Read_Dx  (Address_00_000_D2, Read_Enable_D2, Data_RD2_x, Data_RD2_1)

end unit

unit   "awaretest D3 Test"

 execute Init_State

 call Write_Dx (Address_00_000_D3, Write_Enable_D3, Data_D3_0, Write_Disable_D3)
 call Read_Dx  (Address_00_000_D3, Read_Enable_D3, Data_RD3_x, Data_RD3_0)

 call Write_Dx (Address_00_000_D3, Write_Enable_D3, Data_D3_1, Write_Disable_D3)
 call Read_Dx  (Address_00_000_D3, Read_Enable_D3, Data_RD3_x, Data_RD3_1)

end unit

 unit "Address, Data test"
    execute Init_State
    call Write (Address_Bus_00_000, Data_D_0)
    call Write (Address_Bus_00_001, Data_D_1)
    call Write (Address_Bus_00_002, Data_D_2)
    call Write (Address_Bus_00_004, Data_D_3)
    call Write (Address_Bus_00_008, Data_D_4)
    call Write (Address_Bus_00_010, Data_D_5)
    call Write (Address_Bus_00_020, Data_D_6)
    call Write (Address_Bus_00_040, Data_D_7)
    call Write (Address_Bus_00_080, Data_D_8)
    call Write (Address_Bus_00_100, Data_D_9)
    call Write (Address_Bus_00_200, Data_D_A)
    call Write (Address_Bus_00_400, Data_D_B)
    call Write (Address_Bus_00_800, Data_D_C)
    call Write (Address_Bus_01_000, Data_D_D)
    call Write (Address_Bus_10_000, Data_D_E)

    call Read  (Address_Bus_00_000, Data_R_0)
    call Read  (Address_Bus_00_001, Data_R_1)
    call Read  (Address_Bus_00_002, Data_R_2)
    call Read  (Address_Bus_00_004, Data_R_3)
    call Read  (Address_Bus_00_008, Data_R_4)
    call Read  (Address_Bus_00_010, Data_R_5)
    call Read  (Address_Bus_00_020, Data_R_6)
    call Read  (Address_Bus_00_040, Data_R_7)
    call Read  (Address_Bus_00_080, Data_R_8)
    call Read  (Address_Bus_00_100, Data_R_9)
    call Read  (Address_Bus_00_200, Data_R_A)
    call Read  (Address_Bus_00_400, Data_R_B)
    call Read  (Address_Bus_00_800, Data_R_C)
    call Read  (Address_Bus_01_000, Data_R_D)
    call Read  (Address_Bus_10_000, Data_R_E)
 end unit

 !  *********************************************************************

 ! Check Output Enable
 ! Toggling G_bar btween Hi to Lo with Write_Bar held Hi
 ! for Data output to go between 0 to Z-state to 0
 warning "This test required pullups on pins 17, 16, 15, 14 to"
 warning "test Output Enable pin"

 unit "Output Enable test"
    execute Init_State
    call Write ( Address_Bus_00_000, Data_D_0)
    call Read  ( Address_Bus_00_000, Data_R_0)
    execute Read_Enable
    execute Output_Disable
    call Read  ( Address_Bus_00_000, Data_R_F)
    execute Read_Enable
    execute Output_Enable
    call Read  ( Address_Bus_00_000, Data_R_0)
 end unit

 !  ********************************************************************

 ! Check Chip Enable
 ! Toggling E_Bar between Hi to Lo with G_Bar held Lo
 ! for Data output to go between 0 to Z-state to 0

 warning "This test required pullups on pins 17, 16, 15, 14 to"
 warning "test Chip Enable pin"

 unit  "Chip Enable test"
    execute Init_State
    call Write ( Address_Bus_00_000, Data_D_0)
    call Read  ( Address_Bus_00_000, Data_R_0)
    execute Output_Enable
    execute Chip_Disable
    call Read  ( Address_Bus_00_000, Data_R_F)
    execute Output_Enable
    execute Chip_Enable
    call Read  ( Address_Bus_00_000, Data_R_0)
 end unit

 ! *********************************************************************