+90ns<Min> => "User-controlled sync loop": SyncWhile(reg"LeaderEngine.HVI Quit" != 1) {
    +260ns<Min> => "FPGA Read/Write Operations": SyncMultiSequenceBlock {
        Engine "LeaderEngine" {
            +10ns => "Read FPGA Register_Bank_HviAction4Cnt": reg"LeaderEngine.Action4 Counter" = fpgaReg"Register_Bank_HviAction4Cnt"
            +60ns => "Write FPGA Register_Bank_HviPxiTrigOut": fpgaReg"Register_Bank_HviPxiTrigOut" = reg"LeaderEngine.Action4 Counter"
            +10ns => "Write FPGA Memory Map": fpgaMemMap"MainEngine_Memory_1"[0] = reg"LeaderEngine.Memory Map Counter"
            +30ns => "Read FPGA Memory Map": reg"LeaderEngine.Memory Map Value" = fpgaMemMap"MainEngine_Memory_1"[0]
        }
        Engine "FollowerEngine" {}
    }
    +300ns<Min> => "Wait for HVI_UserEvent4 and Execute HVI_UserAction4": SyncMultiSequenceBlock {
        Engine "LeaderEngine" {
            +10ns => "Read Register_Bank_HviPxiTrigIn": reg"LeaderEngine.PXI Values" = fpgaReg"Register_Bank_HviPxiTrigIn"
            +10ns<?> => "Wait for FPGA_User_Event4": Wait(condition = (event"FpgaUserEvent4"), waitMode = TRANSITION, syncMode = IMMEDIATE)
            +20ns => "Execute Action 4": ActionExecute([action"UserFpga4"])
        }
        Engine "FollowerEngine" {
            +10ns => "Read Register_Bank_HviPxiTrigIn": reg"FollowerEngine.Follower PXI Values" = fpgaReg"Register_Bank_HviPxiTrigIn"
        }
    }
    +10ns<Min> => "Increment counter registers": SyncMultiSequenceBlock {
        Engine "LeaderEngine" {
            +10ns => "Increment memory map counter": reg"LeaderEngine.Memory Map Counter" = reg"LeaderEngine.Memory Map Counter" + 1
            +10ns => "Increment counter register": reg"LeaderEngine.Loop Counter" = reg"LeaderEngine.Loop Counter" + 1
        }
        Engine "FollowerEngine" {
            +10ns => "Increment Follower counter register": reg"FollowerEngine.Follower Counter" = reg"FollowerEngine.Follower Counter" + 1
        }
    }
}
