Keysight Engineering Data Management (SOS) Core: Integration with Cadence Virtuoso

This application note examines the critical role of design data management within the Cadence Virtuoso environment, a widely used platform for analog, RF, and mixed-signal IC design. With tens of thousands of engineers relying on Virtuoso for core design activities, effective data management is essential to ensure design integrity, maintain predictable tapeout schedules, and support team productivity in increasingly complex, collaborative projects.

Keysight Engineering Data Management (SOS) Core introduces a native, deeply integrated data management layer within Virtuoso. This application note details how SOS Core embeds essential version control functions — such as check-in/check-out, update, diff, tagging, and audit trails — directly into the Virtuoso Library Manager and editor interfaces. By eliminating the need to switch between separate tools, engineers can manage design data seamlessly within their existing workflows, improving efficiency and reducing the risk of errors.

The note further explores the integration architecture and illustrates typical day-to-day designer workflows enabled by SOS Core. Advanced capabilities, including Visual Design Diff (VDD), provide detailed visibility into design changes, while hierarchical operations streamline complex design management tasks. The Labels/RSO system facilitates cross-functional collaboration by automating key handoffs in analog and mixed-signal design processes.

In addition, the application note highlights the Links-to-Cache architecture, which delivers high-performance access to design data with minimal storage overhead, regardless of team size or geographic distribution. Customization features also allow CAD teams to tailor the integration to specific organizational processes and requirements.

SOS Core transforms Cadence Virtuoso into a fully data-managed platform. By combining deep integration, robust version control, and scalable performance, SOS Core enables semiconductor design teams to enhance collaboration, ensure traceability, and efficiently manage the growing complexity of modern IC design in the AI era.