Design Simulation and Validation Challenges of a Scalable 2000 Amp Core Power Rail

Webinars

Massive processors for big data, AI, and 100+ Gigabit communications are already reaching 2000 Amps on their core power rails. The next generation of AI/ML ASICs will reach 5000 Amps in just a few more years. This presentation will discuss critical aspects of designing, simulating, and measuring high-current power rails and assessing available topologies to balance performance and cost trade-offs. You will learn how to:

 

  • Simulate with multi-phase parallel VRM models to predict PDN impedance and large and small signal responses in the time domain.
  • Include PCB EM models for DC IR drop, thermal, and AC decoupling to analyze the smallest PCB artifacts and the impact on the desired micro-ohms target impedance.
  • Measure and validate the 2000 Amp power rail using a unique ultra-high-speed transient step loader with ns response times to reach 100% duty cycle for testing thermal and electrical design limits.