Separating Read & Write Signals for DDR DRAM & Memory Controller
应用文章
The second and third generations of Double Data Rate (DDR) memory continue to improve on data rates, but these performance enhancements bring some interesting test and measurement challenges. Analyzing the signal integrity of DDR signals requires differentiating the complex traffic on the data bus to independently measure the signal performance for both the DDR chip and the memory controller.
One of the most challenging measurement issues is separating the read and write signals, given that read and write data transfers are bidirectional on the same data bus (Figure 1). Read data transfer comes from the DRAM chip, whereas write data comes from the memory controller.