DDR4-compliance_demo

This video demo provides a detailed guide on successfully conducting timing tests on SDRAM devices using the DDR4 compliance test application on an Infiniium real-time oscilloscope. The tutorial addresses the common failures encountered during these tests and introduces an approach to mitigate these issues. This involves identifying the appropriate burst triggering technique and threshold settings to ensure the test application can find valid bursts and execute timing tests effectively.

The tutorial then demonstrates a test run on an LPDDR4 test signal with a data rate of 3200 MT/s. It explains the standard approach to running compliance or custom mode tests on a DDR4, LPDDR4, or LPDDR4X SDRAM device. This involves configuring the SDRAM type and speed grade, retaining the default settings for burst triggering method and threshold settings, and selecting the desired tests to run from the Select Tests tab.

In this demonstration, the Write Preamble and Read Preamble timing tests are selected. The tutorial emphasizes the importance of retaining the default settings in the Configure tab, particularly for the signal and channel thresholds, along with other configuration options.

Next, the tutorial guides viewers on how to ensure that the device under test is connected as per the instructions specified in the Connect tab. It stresses the importance of ensuring that the physical setup matches the connection diagram displayed.

To run the selected timing tests, the tutorial instructs viewers to connect channel one of the oscilloscopes to the differential clock pins of the LPDDR4 device under test. It then guides viewers to connect channel two of the oscilloscope to the differential data strobe pins and connect channel three to the DQ pin and ground pin of the LPDDR4 device.

After validating the physical connections, the tutorial runs the selected tests. It highlights the potential issues that may arise during test runs with the default burst triggering method and threshold settings. Specifically, it notes that the application may fail to find any valid write burst required for the write preamble timing test and a valid read burst for the read preamble timing test, leading to failures in the selected timing tests.

To address this issue, the tutorial introduces identifying the appropriate burst-triggering technique for such tests. It demonstrates this by considering two sets of DQS signals to see how the read-write bursts appear on each set and how to determine the burst separation method.

The tutorial concludes by encouraging viewers to extend the fundamental concepts shown in the video to study the characteristics of other test signals. This will enable them to configure the DDR4 compliance test application properly and run tests successfully.