技术资料
As the demand for higher data rates in AI and data center networks accelerates, the industry is transitioning toward 800GE and 1.6 Terabit Ethernet (1.6T) network interconnects and beyond. Interfaces operating at 212Gb/s, 106Gb/s and 53Gb/s electrical lanes and above are critical to meeting higher bandwidth and throughput network infrastructure requirements. Network infrastructures must deliver increased bandwidth while optimizing power consumption and cost per Gigabit. Emerging standards such as OIF-CEI, IEEE 802.3 for 400GE, 800GE and 1.6T pluggable MSAs, define a broad range of high-speed fiber and copper interconnect types. These industry standards set the stage for high-performance solutions capable of meeting stringent devices and interconnect error-performance criteria required in advanced, high bandwidth, network equipment and-network interconnect infrastructure applications.
The Keysight multiple lane Functional Interconnect Test Solutions (FITS-16CH) provides 16 Tx and 16 Rx channels of functional BER and Forward Error Correction (FEC) error performance validation. The FITS-16CH system addresses error performance validation at 212Gb/s, 106Gb/s, and 53Gb/s electrical lane speeds that use four-level Pulse Amplitude Modulation (PAM4) signaling. It is designed for active and passive electrical and optical interconnects such as Active Electrical Cables (AEC), Active Copper Cables (ACC), passive Direct Attached Cables (DAC), Active Optical Cables (AOC), and high-speed, fully retimed (FRO), Linear Retimed (LRO, or RTRL), and Linear Pluggable Optics (LPO) optical transceivers.
FITS-16CH delivers exceptional signal integrity over all channels, freeing up critical design margins to provide clear insight into the performance of your high-speed device and interconnect designs. Whether you are developing next-generation interfaces or tackling the challenges of error performance validation, Keysight empowers you with the precision and reliability required in this rapidly evolving landscape.
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