Confirm Your Country or Area
- Canada (English)
- Canada (Français)
- United Kingdom
- United States
- Hong Kong, China
- Switzerland (French)
- Switzerland (German)
Confirm your country or area to access relevant pricing, special offers, events, and contact information.
- Use elastic virtual test solution with support for globally distributed users
- Generate traffic towards all ports in the design under test at any port speed between 1GE and 400GE
- Access powerful rate measurements and statistics, including granular 1ns latency measurements based on emulation time
- Generate custom Ethernet traffic with hundreds of predefined packet templates
- Support many hardware-based features, including PAUSE, PFC, IP/TCP/UDP checksum generation, CRC error injection, and packet sequence checking
- Ensure zero packet loss between virtual IxVerify and the emulation system
- Share test configurations and scripts across Ixia-based pre-silicon and post-silicon test environments
- Support automation with REST, TCL, Perl, Python, and Ruby
Problem: Network Chip Design Verification Happens Too Late in the Development Cycle
Trends like increased use of UHD video, cloud computing, and 5G-based smartphones are pushing the boundaries of network capacity. To support this demand, network equipment and semiconductor manufacturers are driven to provide ultra-high-speed devices powered by state-of-the-art application-specific integrated circuit (ASIC) and system-on-a-chip (SoC) solutions.
Delivering an Ethernet switching ASIC capable of managing terabits of traffic on hundreds of ports or SmartNIC devices able to support diverse network services is a costly and lengthy process. Given the trend towards larger chips together with ever-increasing time-to-market pressures, all manufacturers are aggressively seeking to optimize and shorten development cycles. Enabling software teams to bring-up chip drivers and SDKs in parallel with hardware design and verification is key to meeting challenging project milestones. Additionally, testing Ethernet packet processing prior to tape-out and avoiding costly re-spins is equally critical to ensuring successful projects.
IxVerify deployment in an emulation-based design verification environment.
Solution: Shift Testing to the Left with Virtualized, Scalable Pre-Silicon Chip Validation
IxVerify is the industry’s only test solution purpose-built for pre-silicon verification. With IxVerify, Keysight and its partners are leading the way in transforming the EDA market by offering virtualized design verification solutions that work in conjunction with next-generation verification flows—leveraging virtualization to reduce dedicated and specialized hardware costs while offering increased flexibility.
IxVerify extends Keysight’s intellectual property and test expertise into the EDA space. It enables new and improved test methodologies to simplify hardware design verification, fuels greater collaboration between hardware and software teams, and enables initiatives to shift all aspects of the product lifecycle to the left.
IxVerify provides hundreds of predefined packet templates for testing Ethernet and TCP/IP protocols and is capable of generating high volumes of traffic. With its ability to run hundreds of virtualized test ports at once, it offers the unique ability to verify the largest chip designs with dynamically shaped traffic, ensuring zero packet loss at maximum emulation speeds.
Data Sheets 2020.05.24
IxVerify – Industry’s Only Solution Purpose-Built for Pre-Silicon Testing
Data Sheets 2020.06.01
IxNetwork® Virtual Edition (VE) Virtualized Network Performance Testing
Product Tour 2017-08-29
IxVerify for Network Equipment Manufacturers and Chip Makers with VP of Business Development, Scott Westlake
Solution Briefs 2019.02.28
Cadence + Ixia: Solutions for Ethernet Network Processor Design Verification