PCI Express® Receiver Testing With J-BERT (Revision 2)

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Introduction

Data rates in the digital communication arena have crossed 10 Gb/s since long. Nowadays, computer buses and interfaces are on their way towards this speed class. PCI Express as an example, which is used as interface bus between CPU, bridge chips and the related peripherals (see Figure 1) is aiming at 8 Gb/s with its third generation.

Making such systems work reliably requires careful design of the related standards and thorough testing of the components that comprise these systems, i.e. ASICs, motherboards and add-in cards.

This document describes in-depth, how to verify current PCI Express rev. 2.0 5 Gb/s add-in cards with respect to the relevant CEM standard using the PCI-SIG® provided compliance base board and Keysight Technologies, Inc. J-BERT N4903A high-performance serial BERT. A step-by-step procedure is given for calibration of the required test signal and the compliance test itself; measurements beyond the pure RX-compliance tests are introduced at the end of this document. If this topic is your only interest, just read section 4 “Compliant test for add-in cards”, starting on page 13.

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