Lesson 1 - Standards Overview

The UCIe 1.1 Specification - Building an Open Ecosystem of Chiplets for On-Package Innovations UCIe vs BoW: Choosing the Right Chiplet Standard Considerations to Successfully Integrate Chiplets in Designs

Lesson 2 - Chiplet Analysis Challenges and Solutions

Chiplet System Analysis Challenges and Solutions Fast Track Chiplet Integration with Streamlined UCIe's Electrical Layer Analysis How-to-Detect-Signal-Integrity-Issues-in-Chiplet-Designs-Early

Lesson 3 - Chiplet PHY Designer

Optimizing UCIe Implementations in Multi-Die High-Speed Digital Designs Building an Interoperable Chiplet Ecosystem through Golden Die Validation with Pre-Silicon Correlation Analyzing Die-to-Die Interfaces In Multi-Die Designs

Lesson 4 - Designing for Advanced Packaging

Introducing the 3D Interconnect Designer Chiplet 3D Interconnect Designer Demo Video 3D Interconnect Designer: Physically Accurate Design and Exploration of Advanced 2.5D and 3D Interconnects Webinar: How To Design Advanced Package Interconnects Without Hatched Ground Simulation Bottlenecks

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Course Level : Advanced

Designing with Chiplets and Advanced Packaging to build system-on-chips (SoCs)

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About the Bootcamp

Learn the basics of designing with Chiplets. Chiplets are a promising alternative to monolithic System-on-Chips (SoCs) that offer lower costs, higher performance, and greater flexibility. Chiplets are also a key enabler of heterogeneous and modular SoC design, which can accelerate innovation and adaptation in the electronic industry.

Audience

This boot camp is ideal for high-speed digital design engineers and anyone seeking a deeper understanding of designing with Chiplets with Electronic Design Automation (EDA) software.

Learn

The current standards framework for Chiplets
How to Optimize UCIe Implementations
The Chiplet system analysis challenges and solutions

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