Keysight and Rambus Collaborate to Detect Pre-Silicon Side-Channel Leakage in AES Design

Keysight and Rambus collaborated to demonstrate that side-channel vulnerabilities in an Advanced Encryption Standard (AES) design can be detected at the pre-silicon stage. Rambus selected a pre-release version of one of its AES designs, in which an SCA vulnerability had previously been identified through traditional Field-Programmable Gate Array-based (FPGA) validation testing. Using Keysight Inspector Pre-Silicon SCA, the Keysight Device Security team identified side-channel leakage from AES design signals directly from simulation, along with its root cause, without needing physical hardware.  The results closely matched traditional FPGA validation performed by the Rambus team.

As cryptographic implementations grow in complexity, identifying vulnerabilities earlier in the design cycle has become a critical priority. Catching issues at the pre-silicon stage reduces the risk of costly silicon re-spins, shortens time-to-market, and eliminates the need for costly physical test equipment. This gives semiconductor and IP designers a faster, more scalable path to side-channel-resistant silicon.

Addressing the Challenge of Early-Stage Security

Creating cryptographically secure silicon is one of the most demanding tasks in hardware engineering. Side-channel attacks, which exploit unintended signals such as power consumption or electromagnetic emissions rather than flaws in the algorithm itself, can undermine even a mathematically sound implementation. Traditionally, identifying these weaknesses has required physical hardware and has often occurred too late in the design cycle, making it challenging to avoid significant rework.

Rambus had previously identified a side-channel vulnerability in a pre-release version of one of its AES cores through FPGA-based validation testing. The challenge was to determine whether the same vulnerability could be detected at the register-transfer level (RTL) and simulation stages, with no physical hardware, and whether its root cause could be isolated directly within the design.

Pre-Silicon Analysis That Delivers Physical-Level Insight

Using Keysight’s DS2210A Inspector Pre-Silicon SCA, Keysight's Device Security team analyzed the pre-release Rambus AES design to independently detect the known leakage and identify its origin, without relying on physical devices or lab equipment.

The results found that the same side-channel leakage observed in FPGA testing was identified at the pre-silicon stage, its root cause was accurately located within the design, and detection was consistent across both RTL and gate-level simulations. The results of the analysis closely matched traditional post-silicon validation methods. Validation of the final release version confirmed that Rambus's mitigations had fully resolved the vulnerability.

Gilbert Goodwill, Technical Director, Engineering at Rambus, said: “Keysight’s Pre Silicon SCA simulation provides a significant improvement over hardware based (FPGA or ASIC) testing by locating the underlying code associated with detected leakage. This is a major improvement compared to hardware-based testing done in isolation of code. The fact that this tool can simulate code close enough to see the leaks, do so with enough performance to make this useful, and now provide this leakage to code connection makes this very significant for developers of side channel resistant intellectual property.” 

Integrating Security Earlier in the Design Flow

The case study highlights a broader shift in how the semiconductor industry is approaching hardware security. Traditionally, side-channel evaluations have been conducted late in the development cycle, after synthesis and often after tape-out, when the cost of fixing vulnerabilities is highest. FPGA-based pre-silicon testing brought evaluations earlier, but still required physical hardware, calibration of measurement setups, and equipment maintenance.

Keysight’s Inspector Pre Silicon SCA takes this further by enabling fully simulation based analysis. It removes hardware dependencies, delivers deterministic and repeatable results, and requires fewer traces. Because it operates directly on RTL and netlist designs, it can be integrated into the design flow and rerun after each change, supporting iterative, data driven security development.

Importantly, it complements FPGA workflows by helping identify potential leakage early, allowing teams to focus on physical validation where it matters most.

Earlier Answers, Fewer Costly Re-Spins 

As security requirements tighten across semiconductors, automotive, aerospace and defense, and more, the ability to catch and address vulnerabilities early is becoming a defining advantage. Keysight Inspector Pre-Silicon SCA gives design teams a faster, more precise path to tape-out, reducing the risk of costly re-spins, shortening time-to-market, and building greater confidence in the security of every cryptographic implementation.

Read the full case study to explore the methodology and technical results in detail.