Forward Clocking – Receiver (RX) Jitter Tolerance Test
Publication Number: 5990-3575EN
Publication Date: 2017.12.01
Language: English
Application Notes

Forward Clocking – Receiver (RX) Jitter Tolerance Test

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Introduction

J-BERT N4903B highperformance serial BERT with complete jitter tolerance testing for forward clocking topologies

  • All jitter sources built-in (DJ, RJ, ISI, SI)
  • Half-rate clocking wit duty cycle variation
  • Common and differential mode interference
  • Flexible pattern sequencer
  • Automated measurements for RX and TX physical layer parameters

This document describes the receiver (Rx) jitter tolerance test requirements resulting from forward clocking topologies. It explains how these requirements can be efficiently fulfilled for compliance and characterization test by using the Keysight Technologies, Inc. J-BERT N4903B high-performance serial BERT with complete jitter tolerance testing. Traditional synchronous clock distribution reaches a limit at several hundred megabits per second (Mb/s.) As the data rate goes up, setup and hold times become increasing critical, particularly given the manufacturing tolerances of chips and PC boards.