Designing 800G Backplanes Using Channel Operating Margin (COM)
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The proliferation of high performance/low power semiconductor chipsets for the data center, enterprise networking, and high-performance computing markets has driven tremendous growth within the internet infrastructure eco-system. New innovative Serializer-Deserializer (SerDes) technologies must deliver the bandwidth, scalability and end-to-end signal integrity needed to meet the demands of advanced networks up to 800G with single-lane 28Gbps, 56Gbps, or 112Gbps serial connectivity. In order to make these hyperscale networks a reality, the physical layer architect designers are turning to new test methodologies. Transmitter and receiver chipsets can employ traditional eyeopening techniques such as Decision Feedback Equalizers (DFE), but newer methods such as Channel Operating Margin (COM) must be used to realize the fastest channels.