PathWave ADS Memory Designer

Challenges of Memory Design and Next-Generation Memory Standards 

Have you spent hours setting up your memory simulations? Remember individually wiring each connection for an entire data bus?
 

Are you worried about the requirements of next-generation memory, such as DDR5, and LPDDR5?

Have you ever worried that crosstalk isn’t being captured accurately enough in your simulations?

Do you want to explore design constraints for your memory channel with vias and transmission lines, optimized for your substrate stack-up, early in your design cycle?

Designing a DDR memory system is already a very challenging and complicating task. It may take hours to setup your simulation, including wiring, setting up IBIS and channel models, as well as design parameters (if you are still using legacy tools and flows). As design margins continue to shrink, and complexity increases, the memory design workflow also need to evolve. With emerging new standards, such as DDR5/LPDDR5, there are new simulation requirements and methodologies to consider. DDR5, as an example, compared to previous generations of DDR standards, now requires equalization at the receiver. This brings the need for accurate IBIS-AMI models for the receiver. Additionally, since project timelines are now tighter than ever, it is essential to design your DDR system in the most predictive and productive manner, reaching design sign-off with the utmost confidence.

DDR5 and LPDDR5 are disruptive technologies:

• Data rate is increased to 3200 – 6400 MT/s (with a view to 8600 MT/s)

• Equalization (including CTLE and DFE) is utilized in both memory controller and DRAM to mitigate ISI (inter-symbol interference)

• Timing and voltage margins are specified at an extremely low BER

Simulation Workflows Need to Evolve for DDR5 and LPDDR5 

1.     Design Margins are Shrinking

As speed grades continue to increase, the unit intervals (UI) we need to work with are continuing to shrink. This leads to jitter eating up a greater portion of your design margin, and we need to carefully handle the cross talk to minimize eye closure. So much so, that at DDR5 speeds, after the long channel, looking at the package pins of the DRAM, the eye may be completely closed. Therefore, equalization to open the eye both at the driver and receiver may be unavoidable. Additionally, design specifications are becoming more bit error rate focused, moving away from traditional setup and hold timing measurements.

2.     Design Complexity is Increasing

With DDR5 and LPDDR5, it is the first time to have decision feedback equalization (DFE) on the DRAM. Traditionally, the DDR specification was at the balls of the DRAM package. With DDR5, probing at the package, the eye can be closed, meaning the receiver specification must move inside the die (after the equalizer). Typical equalization in memory systems are 3 tap pre-emphasis, feed forward equalization for the transmitter, and CTLE, VGA, and DFE for the receiver. 

3.     Project Timelines are Tighter than Ever

It is necessary to have a predictive and productive design flow to minimize the risk of design failure in the first prototype. By reducing design iterations, you can get your product to market as fast as possible.

Additionally, you can increase your confidence in the design sign-off by performing an automated DDR compliance test, powered by Keysight’s industry proven compliance test solutions and measurement science.