PathWave ADS Memory Designer Turbocharges Design Exploration for Broadcom

Efficient Simulation with Better User Experience

Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) and similar high-speed interfaces are commonly at the heart of consumer, data center and industrial devices. For each new device generation, engineers need to explore transceiver and layout design parameters to find the best solutions for signal integrity and reliability. Among these parameters are layout topology and termination, driver settings, channel encoding and equalization.

When designing new products that must perform and meet the physical requirements of customers (size, shape, EMC compliance etc.), how can you quickly and more efficiently explore the options before engineering costs exceed the project’s value? How can engineers avoid dead-ends in the design cycle? The answer lies in design exploration, a key motive for simulation.

Companies have spent decades developing great engineering experience that enables specialists on staff to more quickly decide which design variations to explore. At Broadcom, there is such a global community of signal and power integrity (SI/PI) engineers across a diverse set of business groups.

One of Broadcom’s SI/PI engineers is Jim Antonellis, a member of the Application Specific Integrated Circuit (ASIC) Products Division (APD). APD were seeking a superior path to perform design explorations for cutting-edge semiconductor and PCB layout design. For this, they turned to Keysight PathWave ADS with Memory Designer. Memory Designer enabled a dramatic improvement in effectively exploring all the design options for cutting-edge DDR interfaces – in silicon, package, and PCB layout.

Challenge: Accelerate design exploration

Broadcom APD excels in custom ASIC design. What sets them apart is their skill for designing for any market segment as a service to their customers. APD designs typically require high speed interfaces including DDR4/5, LPDDR4/5, HBM2/3 and newer memory interfaces, and other high-speed device interconnects. The team’s specialized SI/PI engineers need to explore as many design variables as quickly as possible.

APD signal and power integrity engineers were using industry-standard tools to simulate and characterize models for silicon (TX/RX and equalization), channel (PCB, interposer, package) and device configurations (termination, drive strengths and more). However, they wanted to improve efficiency and find answers to broader scenarios more readily.

They desired to replace a cumbersome point-tool approach with a software solution that enables all exploration in one environment with a better user experience.

A frequent issue with the traditional SPICE based approach is that results are idealized, not at all close to real-world manufacturable silicon or PCB substrate. To get accurate results with SPICE, engineers must predict and include complex parasitic elements, stochastic signal models, and injected noise and distortion that more closely represent the real-world circuitry, a time consuming and error prone process. The ability to easily push into a block and define it to a physical level is required, but not at the expense of ease of use. Accurately defining the constituent blocks and analysis needs to be simple and accessible under one GUI.

Solution: Easy block-based design

APD selected PathWave ADS with Memory Designer. Memory Designer stood out not only for its ease of use, but also because of the wide scope of building blocks (PCB to Silicon) and extensive parameter sweeping. It enabled APD to meet current and future needs more completely than any other solution.

Using Memory Designer’s block-based design setup shown in Figure 1, APD was able to rapidly begin simulations with different settings using DDR4, DDR5, LPDDR4, LPDDR5, GDDR6, HBM2, and HBM3.

The primary figure of merit for the SI/PI engineer is the eye diagram seen in Figure 2. The idea is to explore different equalization types as well as different pre-layout interconnect schemes to best determine DDR interface design parameters as well as what would be recommended for Tx/Rx I/O cells and PCB/package layout for best results in the product design.

Using the Memory Pre-Layout Block, APD engineers were able to rapidly configure and simulate parameter sweeps for PCB trace impedances, impedance discontinuities and topology. For the evaluation, they concentrated on the TLINP transmission line model as it gave accurate results with the parameters they needed for variations.

APD conducted trials of different topology schemes including tee, tree/branch, and fly-by as well as point to point. These are the PCB layout topologies most frequently used with DDR in consumer and industrial designs, and lead to very difficult trade-offs. For example, when splitting a transmission line from one memory controller’s transmitter to multiple DRAM receivers, each branch forms an impedance change. This could be accommodated using impedance transformers but comes at the cost of larger trace widths and insertion loss towards the DRAM receiver. By constructing these scenarios in Memory Designer, APD can easily find the optimal trade-offs between SI (insertion loss, eye closure), PCB routing density, and transceiver driver strength or power consumption.