From Overwhelmed to Optimized: SECO's PCB Design Cycle Evolution

Summary

In this case study, we discussed the impact of Keysight's Electrical Performance Scan (EP-Scan) on SECO's design workflow. EP-Scan has effectively relieved the burden on their limited signal integrity engineering team while enhancing the efficiency of SECO’s printed circuit board (PCB) design process.

By transferring the responsibility from signal integrity (SI) engineers to empowering hardware engineers to perform SI analysis on PCBs, EP-Scan notably increases efficiency and teamwork collaboration.

With a simplified and accessible solution, SECO reduced the workload on the Signal Integrity engineers. SECO experienced increased productivity, faster project turnarounds, and greater flexibility in managing design challenges.

Challenge

At the final stage of the product design cycle, the signal integrity engineers verify the performance of the PCB designs. As the number of PCB designs at SECO rises, the signal integrity engineers who perform final verifications become overwhelmed.

Solution

Keysight’s Electrical Performance Scan (EP-Scan) was developed to simplify the SI analysis of PCB designs. SECO’s hardware engineers use EP-Scan to analyze signal integrity on mid to low-complexity designs. These mid to low-complexity boards usually operate at lower data rates but still require signal integrity verification.

With a minimal learning curve, EP-Scan facilitates SECO’s engineers in importing design-for-manufacturing file types (ODB++ and IPC-2581 formats) and analyzing the impedance and S-parameters of selected nets, see Figure 1.

SECO’s favorite EP-Scan feature is the speed of the simulation. EP-Scan’s intelligent trace traversal algorithm makes appropriate assumptions about the PCB designs to provide reliable simulation results with minimal wait time. The algorithm also detects return path discontinuity and via stub resonances, making EP-Scan a productivity booster.

Because EP-Scan uses test plans to make it straightforward to re-run analysis on a new version of a design, SECO engineers can quickly verify the performance of a new design without repeating the simulation setup every time.

By conducting signal integrity analyses on lower complexity designs without depending on signal integrity engineers, SECO conserves engineering resources and maximizes design productivity.

Results

By embracing EP-Scan, SECO harnessed the full potential of its engineering resources, leading to streamlined processes and delivering exceptional value to its customers. SECO reported an approximate 25% productivity increase after integrating EP-Scan.

In addition to the workload reduction for the SI engineers, the hardware engineers in SECO find EP-Scan helpful in analyzing designs.