Accurate PCIe Reference Clock Jitter Measurements
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Jitter Requirements are Becoming Tighter
As the data rates in high-speed digital designs increases, the jitter requirements are becoming tighter. For example, PCIe Gen5 introduces data rates up to 32 GT/s with a reference clock jitter limit of 150 fsec rms. Signal source analyzers are becoming a popular choice for these measurements, due to the inherently lower noise floor compared to oscilloscopes.