Using PathWave FPGA with the M5200A PXIe Digitizer

Keysight's PXIe chassis and M5000 Series modules combined with PathWave FPGA software form a powerful platform for customizing and accelerating test and control systems.  The M5200 digitizer, M5301 baseband digitizer, M5300 AWG, and M5302 digital IO modules have FPGAs with a customer accessible region that can be reconfigured using the PathWave FPGA software. 

Users often want to develop and simulate designs or leverage existing code outside the PathWave FPGA environment.  This application note will show a simple example design that includes custom Verilog HDL that includes Vivado IP written outside the PathWave FPGA application and imported into the design.  Python code to test the design is presented.

The example design used in this app note consists of a Verilog application block designed and simulated independent of the PathWave FPGA environment.  The application is implemented in the user configurable sandbox region of the FPGA in the M5200A four channel 4.8G sample per second digitizer.  Python code is presented to load the sandbox and write to control registers within the sandbox.

The Verilog application multiplies the samples from channel 1 and channel 2 using Vivado multiplier IP and calculates the absolute value of channel 1.  The Verilog application is imported into PathWave FPGA and connected to the reconfigurable FPGA sandbox region.

Channel 1 and channel 3 digitizer data is sent to the sandbox channel 1 and channel 2 sandbox outputs for storage in acquisition memory.  The product of channel 1 and channel 2 is sent to the channel 3 sandbox output and the absolute value of channel 1 is sent to the channel 4 sandbox output for storage. 

Control registers are conveniently implemented using PathWave FPGA IP.  This allows the registers to be easily accessed from the controlling program software by name without having to know the physical address within the sandbox.  The example design has two control registers.  One register enables or disables the absolute value function.  The other register drives the trigger outputs from the sandbox to enable acquisitions.

The approach used in the Python code is to write a Python class with functions to control the module and sandbox designs.  The Python class functions are called by a test function.  This approach allows the class to be imported into larger systems after testing.  Functions in the class can be called from the larger system code after testing the sandbox.  The Python program loads the reconfigurable FPGA sandbox region, digitizes, and stores the outputs of the sandbox.  The FFT of the output signal is calculated using the Python Numpy package and results are plotted using  the Python Pyplot package.