New LDMOS Model Delivers Powerful Transistor Library— Part 1

This new LDMOS model accurately predicts both small-signal and nonlinear performance, and is scalable for devices of different sizes and power output capabilities

 Anew LDMOS transistor model has been developed as a collaboration between W.R. Curtice Consulting, Modelithics and Cree Microwave. This article, the first of a two-part series, describes the background and development of the model. The model has been shown to scale well and fit signal, power and distortion performance for a wide range of device sizes.

 Introduction Non-linear transistor models are being increasingly utilized and demanded by the power amplifier design community because they provide access to multiple simulator capabilities, including DC analysis, as well as analyses of small-signal, nonlinear, time domain, and complex modulation effects. The availability of accurate, validated models eliminates the need for designers to make their own source and load pull and S-parameter measurements on every device, and allow fast “what-if” analysis e.g. change frequency band, drain voltage etc. Savvy semiconductor marketing departments are also recognizing that more and more design engineers use simulators to minimize design risk, reduce design spins and cut design time. Good models will ultimately sell more product. It is well recognized that excellent power performance and linearity can be achieved at low cost using laterally diffused metal-oxidesemiconductor (LDMOS) transistors. In fact they are the technology of choice for base station applications below a couple of GHz as well as many other RF and microwave applications. Existing LDMOS FET large-signal models show a number of disadvantages. They tend to show poor prediction of IMDs, do not work in the sub-threshold region, lack a dynamic self-heating effect, do not use closedform analytic equations to represent channel current, have complex extraction routines and do not scale well with the number of cells. Balancing the trade-off between linearity and efficiency and designing optimal matching and bias networks requires more accurate LDMOS models with better treatment of these effects. Moreover, increasingly complex digital modulation schemes are placing increased demands on model fidelity through 5th or 7th order distortion predictions. This paper describes a new model that meets this challenge in an elegant and robust way. Part 1 of this paper outlines the topology and methods used to extract and validate a baseline one watt (1 W) cell model against I-V, S-parameter, and loadpull data. Part 2, to be published in the next issue of this magazine, will demonstrate the scaling of the model and integration with package parasitics and thermal models to create a non-linear model library for an entire family of related high power transistor products. A 60 watt Doherty amplifier design example will also be presented in Part 2. The library is now available for multiple microwave electronic design automation (EDA) software tools.  

Conclusions 

This first part of a two-part article has introduced the CMC LDMOS model that was derived to provide comprehensive treatment of LDMOS I-V behavior in the four regions of sub-threshold, quadratic, linear and compression, while also accounting for self-heating, breakdown, non-linear capacitance and careful parasitic modeling. Measured to modeled comparisons have validated the model’s IV, small-signal and non-linear simulation accuracy for a 1 watt LDMOS chip. Part 2 will be presented next month, covering application of the model for a 30-watt transistor, which is used in the design example of a 60- watt Doherty amplifier.