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Boosting Phase Locked Loop (PLL) Design Efficiency

Boosting Phase Locked Loop (PLL) Design Efficiency

应用文章

A phase-locked loop (PLL) technique is widely used in today’s advanced communications and broadcasting systems, and PLL frequency synthesizers are an indispensable part of the system. Recent advances of higher data rates and more channels per unit of bandwidth have accelerated the need for higher performance PLL frequency synthesizers. The requirements of modern PLL synthesizers are becoming stricter in terms of frequency stability, frequency switching speed, phase noise and reliability as well as in size, weight and power consumption. These constraints make PLL synthesizer design more challenging and time-consuming. This application note tells you how to design and evaluate PLL synthesizers more efficiently. Examples also show how related PLL system components such as voltage controlled oscillators (VCOs), reference oscillators and frequency dividers/prescalers are characterized and evaluated.

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