Simulating High-Speed Serial Channels with IBIS-AMI Models
应用文章
Introduction
The Input/Output Buffer Information Specification (IBIS) has been an essential component of the electrical simulation toolbox for nearly two decades. Many design engineers are familiar with the application of IBIS models and for the most part, the models have provided an accurate, easy-to-use alternative to SPICE-based transistor models. In fact, most IBIS models are simple behavioral translations of a vendor’s SPICE buffer model. However, as serial interface bit rates increase, critical limitations with IBIS models have become more acute.
With the current (version 5.0) of the IBIS specification, an important algorithmic modeling component has been added to the conventional behavioral analog IBIS model. Several earlier efforts were made to add a mixed-signal model capability with limited success. IBIS-Algorithmic Modeling Interface (AMI) represents an important milestone in the IBIS mixed-signal evolution.
This paper reviews some of the benefits and limitations of using IBIS models and introduces the new AMI extensions to the latest IBIS version 5.0 specification. Additionally, it illustrates how to perform several simulations of a typical backplane system using the Advanced Design System 2011 (ADS2011) toolset.