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Historically, DDR (double data rate) has defined its timing specifications with a belief of a zero bit error rate (BER). While a zero bit error rate is statistically not possible, timing budgets had enough margin to justify the method of specification and measurement. With each generation of DDR Synchronous Dynamic Random Access Memory (SDRAM), speeds increase, package sizes decrease, and power consumption decreases. (See Table 1). Added challenges come with these improvements of decreased design margins, signal integrity, and interoperability. Latest DDR technology offers data rates of 3.2Gb/s or higher. Each picosecond now matters and can be the difference in passing and failing bits.
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