Active Mixer Design - Chapter 10

Active Mixer Design

PathWave Advanced Design System (ADS)

Taken from Keysight EEsof EDA Technical Note: Low Power Mixer Design Example Using Advanced Design System

Introduction

This chapter describes a method for designing a low-power single-transistor active mixer using Keysight Advanced Design System (ADS). It includes details on the design steps, simulation setups and data displays. The workspace file discussed in this lab is available in ADS. To find it, click the button labeled Open an Example Workspace in the ADS homepage. Under All Examples (in alphabetical order) click example titled MixerPager_wrk.7zads. Chose a workspace to place this file in and then let it unarchive itself. After the file has unarchived, in the list of available files in the folder, open and read the schematic in 01 ReadMe.

Circuit Specifications

The mixer is an upper sideband down converter, with an RF of 900 MHz RF, and a 45 MHz IF. The simplified specifications supplied for this design call for it to provide a 10 dB conversion gain, operating from a 1 Volt DC supply at 600 μA current. This very low power consumption is typical of applications such as pagers and cellular phones, where battery lifetime is critical. Low cost is another driving factor in such applications. Other typical specifications a mixer would have to meet in a “real-world” design, such as linearity, port-to-port isolation, spurious response and noise figure, are not included in this particular example. Open the examples in the workspace Mixers_wrk.7zads for examples of how to include these simulations in your design.

Device Selection

One of the first steps in the design process is to select the device. The device used for this example is the Motorola MMBR941, a bipolar junction transistor (BJT) packaged in a standard SOT-23 plastic package. While bipolar devices do not generally have as good of mixing properties as field-effect transistors, the low operating voltage precludes using FETs in this case. The chosen device has acceptable performance for this application and offers several other advantages: it is extremely low cost, and accurate models are readily available. A rule of thumb in high-volume, low-cost applications is to use the least expensive device that will accomplish the job, the MMBR941 is a good choice for this mixer. It is equally true that, no matter how good a device is, if there are no models with which to simulate it, it becomes impossible to use in a design.

The device model, taken from the ADS RF Transistor Library, is a Gummel-Poon model where the parameters were extracted by the manufacturer, Motorola. Initially, the model’s DC performance is verified by comparing DC I-V curves. Next, a bias network will be designed to establish the desired operating point. The model’s RF behavior will then be checked by comparing the simulated S-parameters with measured S-parameters taken at the same bias conditions. Finally, the model’s nonlinear performance is verified by simulating gain compression and comparing to measured results.

Device Model DC Verification (Cell: DC_curves)

DC_curves (see Figure 3) shows one way to set up a swept-parameter DC analysis. Open the MixerPager_wrk workspace. It is in 02_DC & Bias Point > DC_curves > schematic. The DC voltage supply at the collector is set to a variable, VCE, which is initialized in the VAR block. The VAR block also initializes the variable, IBB, used in the DC current source at the base of the BJT. The actual values used for VCE are determined in the DC simulation controller (DC1). In this example, VCE is swept from 0 V to 6 V, so that the model can be verified over a relatively wide operating range. The DC controller can only sweep a single variable, so the values for IBB are swept using the ParamSweep component. The range chosen for the base current, IBB, is set to 50 to 350 μA. This IV characteristics simulation setup is available as a default template in ADS and designers can obtain the same under Schematic page by selecting Insert > Template > BJT Curve Tracer. It can be used after setting IBB and VCE values as desired by designers.

Device Model RF Verification (Cell: BiasNet)

BiasNet (02_DC & Bias Point > BiasNet > schematic), shown in Figure 10, includes both DC and S-parameter simulations so, in this case, bias tee components (DC feeds and blocks) are required to ensure proper RF performance. DC results are displayed directly on the schematic page, using the DC back annotation feature. Once the simulation has been run, select Simulate > Annotate DC Solution to see the DC voltages and currents at each node. This simulation can be done with both the exact resistor values and nearest standard values (Rc = 470 Ω, Rb = 8.2 kΩ) to confirm that the operating point is correct.

Device Model Large-Signal Verification (Cell: Compression)

Compression (03_Compression & IF Match > Compression > schematic), shown in Figure 12,

shows two ways of calculating the device output compression at the RF frequency of 900 MHz. The

conventional way, implemented here with the Harmonic Balance controller, is to sweep the input power

level from low (i.e. small-signal) to high values until the output power compresses (the ratio Pout/Pin

starts to fall off from its small-signal value). The input power variable, “PwrIn” is swept from -45 to

-5 dBm and a Measurement Equation component is used to define the output power at 900 MHz, in

dBm. Notice that the dBm function assumes the power is being delivered to a 50 Ω load, unless

otherwise specified by the user. The argument of the function, “HB.Vout[1]”, specifies the fundamental

frequency. Figure 13 shows the equation and graph used to determine the 1 dB compression point and

includes the measured results as well.