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Industry adoption of emerging technologies such as 5G and the Internet of Things (IoT) requires data servers and mobile devices to offer faster data rates and performance alongside lower power consumption. Data center operators will transition from 100 gigabit Ethernet (GE) to 400GE to increase network bandwidth for 5G-capable data centers. As data center operators migrate their networks to 400GE, they also need to plan for the next generation of high-speed computing interfaces. Peripheral Component Interconnect Express (PCI Express® or PCIe®) expansion bus will move from PCIe 4.0 to PCIe 5.0, and double date rate (DDR) memory will move from DDR4 to DDR5.
Each new generation of the DDR synchronous dynamic random access memory (SDRAM) standard delivers significant improvements over the previous generation including increased speeds, reduced footprint, and improved power efficiency. However, these improvements introduce new design and test challenges for chip designers and device manufacturers.
The DDR5 standard, defined by the Joint Electronic Devices Engineering Council (JEDEC) organization, will operate at data rates up to 6.0 gigatransfers per second (GT/s) or higher. DDR5 effectively doubles the data rate of DDR4, which supports speeds up to 3.2 GT/s.
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