技术资料
Challenge: Finding Problems Faster and Earlier in the 400GE Development Cycle
400 Gigabit Ethernet (GE) technologies based on the 56Gb electrical lane signaling rates have exponentially increased the level of complexity for the development of stable port electronics in all networking devices. Now, the challenge has become characterizing and quantifying the actual bit error ratio (BER) and forward error correction (FEC) performance of silicon devices, application-specific integrated circuits (ASICs), optical transceivers, fiber and copper interconnects, and the port electronics of switches and routers. Identifying 400GE, 200GE, 100GE, and 50GE BER and FEC performance problems quickly is critical as answers are complex and time-consuming to solve.
Solution: A Simplified, Affordable BERT and FEC Test System
Keysight’s A400GE-QDD test system makes the challenge of qualifying BER on 400GE electronics easier and affordable. Whether validating chips, optical transceivers, or port electronics, the A400GE-QDD is a dedicated BERT and FEC test system with 56Gb electrical lane signaling per port that gives you the ability to find a problem in minutes, not hours. It shows a system-level view of the BER and FEC performance of all the lanes, all at once, in real time.
The A400GE-QDD is a compact BERT and FEC symbol error correction performance benchtop test system. It may be installed on a rackmount as desired. The chassis is provided with the Layer 1 BERT 400GE test software, KiOS. The KiOS single-page application (SPA) uses the Google Chrome browser implementation and makes set up so easy and fast, you can start testing and generating PASS/FAIL test reports using your tolerance and limits within minutes. An optional RS-544 (KP4) FEC symbol error correction test capability is available that simplifies FEC lanes testing, just as easily as Layer 1 BERT. Keysight’s FEC codeword bit-error density distribution analysis (the FEC tail) shows the symbol error performance and other advanced measurements when it comes time to perform long-duration and stress tests; it cannot be made any easier.
The new patented Enhanced BERT option provides your development teams test capabilities to quickly pinpoint problems and to validate and qualify excellent BER and FEC symbol error correction performance:
• In-depth analysis of mismatched PAM4 multi-level signal errors
• SSPRQ100 pattern generation for 100G lane applications (please consult the factory for more information)
• BERT inferred FEC for faster analysis of FEC simultaneously over all Ethernet speeds
• A threshold bit-error tool to expose difficult-to-find bursty errors in PRBS patterns
A400GE-QDD chassis are available in two models:
• 2-port, 400GE Layer-1 BERT QSFP-DD test system (941-0080)
• 4-port, 400GE Layer-1 BERT QSFP-DD test system (941-0081)
o Recommended for use with the Keysight M8040A BERT Analyzer
Pay as You Grow—2-port and 4-port Models, All Field Upgradeable
A400GE-QDD upgrades extend the reuse of the chassis system and improves your ROI. The ability to upgrade A400GE-QDD to have it grow with your test needs is quick and easy. You can field-upgrade any A400GE-QDD 2-port model to a full 4-port model. You can also field-upgrade any 2- or 4-port model to add RS-544 FEC (KP4) test capability to enhance the built-in BERT features.
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