Validate Your PCIe® Designs Faster

Introduction

With the proliferation of PCIe use cases and applications, the need for reliable PCIe protocol debug tools that are deployable quickly has become critical for validation labs.

Protocol validation occurs at the physical layer, data link layer, and transaction layer. In addition to the mandatory protocol compliance tests, the PCI-SIG® recommends more than a hundred additional tests to characterize your design properly. A key area of protocol test is link training and status state machine (LTSSM). Once the physical layer of a PCIe link has enabled the link to train, you need to determine if the data packets transferred between the link partners. You need protocol analysis and exerciser tools to determine if your PCIe device can successfully communicate with its link partner.

Use Case Summary

Some of the most challenging PCIe issues occur during the bring-up sequence. For example, link partners fail to negotiate to the highest mutually-supported speed, links have high bit error rates, links operate in degraded modes, or frequently restart. Having a protocol analysis tool that provides a clear and accurate view of how the protocol and LTSSM are working is important. In designing the Keysight PCIe 5.0 protocol solution, our engineers prioritized signal integrity. Our engineers recognized that reliable  electrical performance is the foundation for a reliable protocol analysis strategy.

Solution Overview

The Keysight PCIe 5.0 protocol solution controls signal integrity using its built-in equalization and amplification that removes the analyzer's effects from the link. These features give the user confidence that the traffic observed between the host system and endpoint is exactly as if the analyzer were not present. 

The Keysight P5552A PCIe protocol analyzer enables deep protocol analysis of PCIe systems in a form factor that is easy to deploy on the lab bench. This solution offers accurate signal integrity. The Keysight P5551A PCIe 5.0 protocol exerciser enables test engineers to emulate the PCIe root complex and endpoint devices when validating PCIe designs. The PCIe protocol testing solution helps you to perform complex protocol tests and quickly debug any detected errors to ensure compliance with your PCIe devices.

Learn more at: PCI Express® Test Overview

Summary

• The key area of PCIe protocol testing is link training and status state machine (LTSSM), to determine if data packets are transferred between the link partners.

• Protocol test strategy needs to consider tight signal integrity margins.

• Lab engineers need reliable PCIe protocol debug tools they can deploy quickly.

For more information: PCIe Protocol Testing