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Better to Think about Your Signal Integrity Early Than Late
The recent USB4 standard release introduced the 3-level Pulse Amplitude Modulation (PAM3), increasing the signal integrity (SI) requirements for the USB4 channels in the printed circuit board (PCB) design [1]. The raised design complexity of USB4 creates a need to perform SI analysis early in the PCB design process to avoid costly re-spins of PCB designs and the delay in the product’s time-to-market. At the beginning of a design iteration, PCB designers and hardware engineers start with a circuit-level schematic design. The schematic is then converted into a PCB layout. At the final stages of the iteration, the signal integrity (SI) engineers are involved in performing signal integrity analysis on the layout. SI engineers provide feedback or recommendations to improve signal integrity, often requiring PCB layout changes. Because USB4 introduces significant design complexity due to its higher data rates, enhanced features, and backward compatibility requirements, the hardware engineers must verify the SI of the layout while working on it rather than relying on the SI engineers when the PCB layout is completed. This application note addresses the unique challenge: verifying signal integrity on a work-in-progress PCB design with USB4 specifications.
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