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Design for test rules (DFT) for in-circuit test (ICT) test pads are well known and have served the industry well for nearly two decades. However, increasing PCB densities continually put pressure on board designers to eliminate ICT testpads. Furthermore, recent technical advances in operational board speeds are leading some designers to believe that ICT test pads cannot be added in the high-speed sectors of boards soon to be designed. Since the effectiveness of ICT is directly related to test pad access, some have questioned the long-term viability of ICT in this high density/high speed PCB environment.
Parker has introduced a new ICT probe technique in 2004 to address these issues [Park04]. Keysight Technologies, Inc. references this technique as the “Medalist Bead Probe Technology”. Parker shows that this new technique will not degrade the high-speed circuit performance of tomorrow’s gigabit logic boards. He also presents test results showing that this new technique can be used with typical PCB assembly processes and ICT fixtures with similar electrical performance and reliability to current ICT probing techniques.
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