Simulation Drives mmWave Design Flow

Nokia Bell Labs Leverages End-to-End Keysight Ecosystem to Develop W-Band Phased-Array System with First-Pass Success

Bringing complex wireless communications to market takes years of research and development. Advanced research into high-frequency millimeter-wave (mmWave) technologies is driving the 5G revolution. Exploration of transceiver technologies for different frequency bands in the wireless spectrum leads to innovations for point-to-point and point-to-multipoint network solutions.

Bell Labs parent Nokia is no stranger to the kind of bleeding-edge work required to make 5G a reality and pave the way for 6G. Engineers in the mmWave Application Specific Integrated Circuit (ASIC) Research Group at Nokia Bell Labs recently completed another milestone in their near-decade-long study of W-band (75–110 GHz) phased-array systems. Nokia Bell Labs’ projects are leading the way to significant cost reduction, which is necessary for commercial adoption of these high-bandwidth wireless system implementations.

The mmWave ASIC research group created a complex W-band system comprising a 24-element phased-array radio-frequency integrated circuit (RFIC) co-designed and assembled onto a printed circuit board (PCB) interposer to produce a scalable phased-array tile. The engineers combined 16 tiles onto a carrier PCB to create a 384-element (256 Tx / 128 Rx) phased-array system with built-in self-alignment and self-test.

The system is one of the most highly integrated mmWave RFIC phased arrays (Figure 1). At W-band frequencies, higher insertion losses make RF distribution increasingly challenging to implement on conventional substrate materials. Nokia Bell Labs’ tiled architecture approach is necessary for creating phased arrays with hundreds of active elements with flexibility in system design based on specific link budgets.

Challenge: Achieving Fiberless Over-the-Air Data Transmission Rates

5G mobile technology requires ultra-low latency and high data rates with widespread deployment that supports multiple users through the use of picocells. Picocells feature hundreds of active elements capable of producing thousands of highly directive beam patterns that form multi-gigabit-per-second wireless links over hundreds of meters.

The group’s highly integrated design approach reduced overall system cost by eliminating expensive external components such as mmWave synthesizers, amplifiers, and switches. The RFIC chipset and system design leverage low-cost, traditional manufacturing techniques without using exotic packaging processes and materials. Nokia Bell Labs engineers designed their system to simplify factory testing. Incorporating features such as self-test, fault detection, health monitoring, and self-calibration into the RFIC avoids the cost of performing mmWave verifications. It also enables remote maintenance and system reconfiguration in case of failures.

Another challenge, from a holistic system perspective, was the nature of 5G technologies. Every aspect of the transceiver design at W-band frequencies is new, so not much reference material was available before the project began. Nokia Bell Labs researchers are exploring new ground, from the silicon and RFIC chipsets through the antenna chips, packaging, and board. Seeing positive initial results from this project and understanding where the rest of the industry is going validates many of the team’s intelligent design decisions at the system level.

Solutions: Simulation Accuracy Ensures First-Pass Success

When it comes to RFIC design, a big problem for the Nokia Bell Labs researchers is the very high frequencies. They have to perform electromagnetic (EM) simulations for major components within a block, then do proper linearity and noise figure and gain simulations on the entire system. The challenge is fitting in all the required simulations on the system-level block containing many subdivisions of smaller blocks with the highest accuracy in a short time frame.

The RFIC chip measures almost a centimeter squared, with 575 interconnects in the package. The team cannot perform on-wafer measurements for the entire chip because of its size. The only place engineers can take measurements is at the interposer level. Therefore, simulation accuracy is critical. The simulations at every level must work correctly to get the whole tile working.

The Nokia Bell Labs team designed the interposer to allow more conventional chip testing at a socket or PCB level rather than with a probe station. The packaged antennas incorporate a fully integrated phased array that interconnects with each RF port on the RFIC. The team routed and designed all the interconnects and antennas on a unique basis in PathWave ADS. Engineers then simulated the design as a whole using PathWave ADS RFPro or PathWave EM Design (EMPro). It is a large, full, 3D EM finite element method (FEM) simulation that takes a long time to complete.

Another big issue the R&D team faced was reaching first-pass success. Limited engineering resources made relying on the accuracy of the simulation software crucial. Because the system is so complex, one small issue can jeopardize the entire budget and two years of effort. Achieving success quickly without design spins means staying in front of the rest of the industry in this competitive space.

Results: Measurements Correlate Closely to Simulation

Nokia Bell Labs’ actual measurements tracked to simulation at every step, from silicon to board-level integration and system enclosure. Since FEM solvers were not practical for board-level simulation, the team exported the board design into PathWave ADS SIPro and PIPro to perform a full signal and power integrity analysis. The board simulation ran more efficiently in SIPro and PIPro. The interoperability between the tools made the transition smooth. With just a click, the team had the full board, completely netlisted and ported. It then chose the nets of interest to see how everything worked together.

The complexity of the phased-array system and the sheer number of connections required to make reliable measurements were significant challenges for the test setup. For example, on the probe station, it took six hours of setup time for the phase-locked loop measurement. If any connections were not right, the setup did not give the right answer. One of the team’s most significant challenges was measuring the S-parameters. Team members made the S-parameter measurements on the probe station using smaller silicon slices of the RFIC building blocks.